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ASIC Emulation Engineer (9640051)

-       Port ASIC/IP RTL to Emulation platforms (Palladium/FPGA)

-       Bring-up and debug the platform issues

-       Write the testplan to meet ASIC pre-silicon and post-silicon verification and validation goals including scenarios, corner cases, performance, etc.

-       Write testcases (SystemVerilog and C bases), execute and debug the failures on emulation platforms

-       Hardware Emulation Platforms and tools

-       RTL development (Verilog/SystemVerilog/VHDL)

-       Simulation acceleration knowledge (DPI and Transactors)

-       Gate-level understanding of RTL and Synthesis 

-       Logic simulation: VCS/NCSIM

-       Programming/scripting skills (C, C++, Python)

-       Software Debug tools (e.g. JTAG/Lauterbach/GDB)

-       Excellent communication skills, and ability to work in a fast-paced exciting environment

 8+ years’ industry experience, BS EE or CE, MS preferred

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