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Design Verification Engineer

  • Write and augment existing testplans.
  • Implement testbench and scoreboards / checkers.
  • Implement test sequences as per plan and debug failures
  • Achieve 100% functional and code coverage
  • Work closely with designers, micro architects & f/w to resolve issues
  • Ability to communicate & articulate clearly progress / issues with project leads
  • 5+ years of proven experience as a DV engineer
    • Implied: Candidate will have hands on Experience with executable test plans and Coverage Driven verification
  • 2+ years of hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)
  • Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
  • Scripting (python, perl or similar)


Nice to Have:

  • SoC level design verification experience
  • ASIC design experience
  • Experience in Computer Graphics & Display Subsystems is desirable


Interview: 30 mins coding screen (SV), 60 min onsite w/Team

  • Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science
  • Master's Degree preferred but not required
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