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ASIC Design Engineer (9462438)
IT/Engineering and Mobile
Seven or more years of experience in logic (RTL) design (modules/sub-systems) for ASICs using Verilog or SystemVerilog
Micro-architecture at module/sub-system/chip-level
Solid understanding of integration of IPs/modules/sub-systems designed by internal/external teams (CPUs, bridges, NOC, etc.)
Experience using AMBA bus protocols
Logic synthesis, timing constraints and low power design methods
Collaborate with the verification team on test plan, coverage and debug
Experience with VCS, Verdi, DC, Spyglass or equivalent tools
RTL (Veriglog/SystemVerilog) for ASIC design
Scripting and programming experience using Perl, TCL, and Make
Strong technical skills
Excellent communication skills.
MS & BS in Electrical Engineering or related field with 7+ years of SOC/ASIC design experience.
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