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Digital Data Path Engineer


·       Implement algorithm blocks as RTL code as defined in the Micro Architecture

·       RTL Implementation and Integration

·       Support Vendor release management

·       Support DV team for verification of blocks

·       Assist with synthesis and timing closure

·       Work with FPGA engineers to perform early prototyping

·       Support handoff and integration of blocks into larger SOC environments

·       Assist with Algorithm analysis, verification and improvement

·       Contribute to ASIC digital architecture, design and verification

·       Ability to document and communicate clearly


·       10-12 years of experience as a Digital Design Engineer

·       Experience with HLS Catapult tool is a big plus but not a must

·       Experience in RTL coding, Lint/CDC tools, synthesis and LEC tools

·       BS Electrical Engineering/Computer Science or equivalent experience


·       HLS coding using Catapult and Xilinx Vivado tools

·       System Verilog OVM/UVM DV experience

·       Python (or similar) scripting experience

·       ASIC design experience

·       Masters Degree in EE

BS or MS in Electrical/Electronics

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